The present disclosure relates generally to the computer memory field, and more particularly, to on-chip testing of dynamic random access memory (DRAM) semiconductor chips.
A DRAM memory cell (memory bit) is a binary memory element formed with one transistor and one capacitor. A modem DRAM memory unit may contain many millions of addressable memory cells. Each cell's capacitor holds binary information in the form of charge, and the cell's transistor operates as a switch to introduce and control the charge stored on the capacitor.
The memory cells are organized into arrays. To access a particular memory cell when performing a read operation, the operator supplies the DRAM with the address of the cell to be accessed. The DRAM translates the address into a row address and a column address of the array the memory cell is located in, and the addressed column and row are then accessed and the charge stored on the memory cell capacitor at the intersection of the addressed column and row is sensed.
FIG. 1 is a diagram showing a memory cell array map for a 4 Meg.times.4 DRAM (i.e., a DRAM with sixteen million total bits, accessible in four million, four-bit units). Array maps for other size DRAMs are similar in content. The DRAM is divided into four quadrants, each made up of a series of rows, such as row 106, and columns, such as column 107. The rows in quadrants one and three have addresses extending from zero to 1023, and are accessed four at a time. That is, because each row address in a quadrant is repeated four times, access to any row address drives four physical rows in the accessed quadrant. Each column in a quadrant, such as quadrant three, intersects all four active rows. The column addresses in quadrants one and three extend from zero to 2047. The addressing scheme is similar for quadrants two and four. For each bit that is eventually output by the DRAM, the active column and the active physical rows access four bits in a quadrant. Additional circuitry on the DRAM selects certain of the four accessed bits and places them on the appropriate output data pin(s). In this example, two bits are selected from the physical rows accessed in quadrant three, corresponding to output DQs 2 and 3, and two bits are selected from the physical rows accessed in quadrant one, corresponding to output DQs 1 and 4.
Before shipping a DRAM semiconductor chip, it must be tested to ensure that all the memory cells function properly. One conventional method of testing a DRAM is to have an external testing device store data in every memory cell in the DRAM, and then read out every memory cell in the DRAM. In this manner, DRAM defects can be detected by comparing the known input data to the output data. However, as DRAMs increase in capacity, accessing all the memory cells begins to take an inordinate amount of time. For example, in the case of a 4 Meg.times.4 DRAM, conventional testing techniques would require four million write cycles and four million read cycles to fully test the DRAM one time.
A second conventional method decreases testing time by taking advantage of the fact that multiple bits are sensed when a row address is accessed in a quadrant. In this method, circuitry is placed on the DRAM chip, which operates on multiple data bits sensed for each row address. The circuitry transmits a logic one if all the sensed data bits are a logic one, a logic zero if all the sensed data bits are a logic zero, and enters a high impedance state if the data bits are mixed, i.e., both logic ones and zeros.
To perform a DRAM test with the second conventional method, the external testing unit, for each column address, writes either all ones or all zeroes to each row address to be tested, and then performs a read operation on the addresses. For each address read by the testing unit, the internal DRAM test circuitry outputs a one, zero, or high impedance state, thus informing the testing unit whether any of the bits sensed in the row address are bad. By testing a plurality of data bits simultaneously, testing time is reduced.
A goal of both of the above described conventional testing techniques is to replace defective addresses when found. One way to do this is to fabricate the DRAM memory arrays with extra rows and columns of cells, which can be substituted for rows or columns of cells found to be defective. Essentially, when a defective row or column is found, fuses are blown, isolating the defective row or column and mapping the redundant row or column to the address previously occupied by the defective row or column. In this manner, a memory array with a limited number of defective elements can be completely repaired. Two types of fuses are commonly used in the repair of DRAMs: laser fuses and electrical fuses. The laser fuse is typically a polysilicon conductor that becomes an open circuit when blown by an externally applied laser beam while the memory die is in wafer form. The electrical fuse is in the form of a capacitor whose plates are short circuited together upon application of a high voltage. The electrical fuse may be activated by repair circuitry internal to the DRAM, even when the DRAM is fully packaged.
The above-described conventional testing and repair techniques require a sophisticated external testing unit, which spends a significant amount of time testing each DRAM. As DRAM sizes increase, the amount of required testing time proportionality increases. For high volume DRAM manufacture, testing time may become unacceptably long.
There is, therefore, a need to reduce the amount of time each DRAM is connected to a testing unit. Additionally, it is desirable to decrease the complexity and expense of external testing units.